Drive circuit

ABSTRACT

The present drive circuit includes: a first N-type transistor connected between a power supply potential line and an output node; a P-type transistor connected between the power supply potential line and the gate of the first N-type transistor; a second N-type transistor forming a diode connected between the gate of the first N-type transistor and a prescribed node; and a differential amplifier for regulating the gate potential of the P-type transistor to match the potential at the prescribed node with the input potential.

TECHNICAL FIELD

The present invention relates to a drive circuit, and more particularly,to a drive circuit in which an electric potential corresponding to aninput potential is output to an output node.

BACKGROUND ART

FIG. 22 is a circuit diagram illustrating the structure of aconventional drive circuit 130. In FIG. 22, drive circuit 130 includes adifferential amplifier 131, a P-type field-effect transistor(hereinafter referred to as a P-type transistor) 132 and aconstant-current circuit 133. P-type transistor 132 is connected betweena power supply potential VDD line and an output node N132. Constantcurrent circuit 133 allows a constant current to flow from output nodeN132 to a ground potential GND line. Differential amplifier 131 has anon-inverting input terminal receiving the potential VI at an input nodeN131, an inverting input terminal receiving the potential VO at outputnode N132, and an output terminal connected to the gate of P-typetransistor 132.

When the output potential VO is higher than the input potential VI, theoutput potential of differential amplifier 131 is increased, theelectric current flowing into P-type transistor 132 is decreased, andthe output potential VO is decreased. When the output potential VO islower than the input potential VI, the output potential of differentialamplifier 131 is reduced, the current flowing into P-type transistor 132is increased, and the output potential VO is increased. Thus, VO=VI.

Unfortunately, since conventional drive circuit 130 has a directfeedback from the output potential VO to differential amplifier 131, theload capacitance may vary when it is large, or oscillation may occurwhen the input potential VI varies.

DISCLOSURE OF THE INVENTION

A main object of the present invention, therefore, is to provide a drivecircuit with reduced oscillation occurring.

The drive circuit according to the present invention is a drive circuitfor outputting a potential, corresponding to an input potential, to anoutput node, including: a first transistor connected between a firstpower supply potential line and an output node; a second transistorhaving a gate and a first electrode connected to the gate of the firsttransistor, and a second electrode connected to a first node; a thirdtransistor connected in series with the second transistor between secondand third power supply potential lines; a first differential amplifierfor regulating the gate potential of the third transistor to match thepotential at the first node with the input potential. Consequently, thecapacitance of the first node is sufficiently small compared with theload capacitance connected to the output node, thereby minimizingoscillation occurring.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing the structure of a push type drivecircuit according to a first embodiment of the present invention.

FIGS. 2A to 2C are circuit diagrams illustrating the structure of aconstant current circuit shown in FIG. 1.

FIG. 3 is a circuit diagram showing a modification of the firstembodiment.

FIG. 4 is a circuit diagram showing another modification of the firstembodiment.

FIG. 5 is a circuit diagram showing the structure of a push type drivecircuit according to a second embodiment of the present invention.

FIGS. 6A to 6C are circuit diagrams illustrating the structure of aconstant current circuit shown in FIG. 5.

FIG. 7 is a circuit diagram showing a modification of the secondembodiment.

FIG. 8 is a circuit diagram showing another modification of the secondembodiment.

FIG. 9 is a circuit diagram showing the structure of a pull type drivecircuit according to a third embodiment of the present invention.

FIG. 10 is a circuit diagram showing a modification of the thirdembodiment.

FIG. 11 is a circuit diagram showing another modification of the thirdembodiment.

FIG. 12 is a circuit diagram showing the structure of a push type drivecircuit with offset compensation capability.

FIG. 13 is a circuit diagram showing the structure of a push type drivecircuit according to a fifth embodiment of the invention.

FIG. 14 is a circuit diagram showing the structure of a push type drivecircuit according to a sixth embodiment of the invention.

FIG. 15 is a circuit diagram showing the structure of a push-pull typedrive circuit according to a seventh embodiment of the invention.

FIG. 16 is a circuit diagram showing a modification of the seventhembodiment.

FIG. 17 is a circuit diagram showing another modification of the seventhembodiment.

FIG. 18 is a circuit diagram showing yet another modification of theseventh embodiment.

FIG. 19 is a circuit diagram showing the structure of a push-pull typedrive circuit according to an eighth embodiment of the invention.

FIG. 20 is a circuit diagram showing the structure of a push-pull typedrive circuit according to a ninth embodiment of the invention.

FIG. 21 is a circuit diagram showing the structure of a push-pull typedrive circuit with offset compensation capability according to a tenthembodiment of the invention.

FIG. 22 is a circuit diagram showing the structure of a conventionaldrive circuit.

BEST MODES FOR CARRYING OUT THE INVENTION

[First Embodiment]

FIG. 1 is a circuit diagram showing the structure of a push type drivecircuit 1 according to a first embodiment of the present invention. InFIG. 1, drive circuit 1 includes a differential amplifier 2, a P-typetransistor 8, N-type field-effect transistors (hereinafter referred toas N-type transistors) 9 and 10, and constant current circuits 11 and12.

Differential amplifier 2 includes P-type transistors 3 and 4, N-typetransistors 5 and 6, and a constant current circuit 7. P-typetransistors 3 and 4 are connected between a power supply potential VDDline and respective nodes N3 and N4, and have their gates commonlyconnected to node N4. P-type transistors 3 and 4 form a current mirrorcircuit. N-type transistors 5 and 6 are connected between respectivenodes N3 and N4, and node N5, and have their gates receiving thepotential VI at input node N1 and the potential VM at node N9,respectively. Constant current circuit 7 is connected between node N5and a ground potential GND line and allows a constant current I1 with aprescribed value to flow from node N5 to the ground potential GND line.

P-type transistor 8, N-type transistor 9 and constant current circuit 11are connected in series between the power supply potential VDD line anda ground potential GND line. P-type transistor 8 has its gate receivingthe potential V3 at output node N3 in differential amplifier 2. The gateof N-type transistor 9 is connected to its drain. N-type transistor 9forms a diode. Constant current circuit 11 allows a constant-current 12with a prescribed value to flow from node N9 to the ground potential GNDline. The potential VM of the source of N-type transistor 9 (at node N9)is supplied to the gate of N-type transistor 6. N-type transistor 10 isconnected between the power supply potential VDD line and output node N2of drive circuit 1 and has its gate receiving the potential VC at nodeN8 between transistors 8 and 9. Constant current circuit 12 is connectedbetween output node N2 and a ground potential GND line, allowing aconstant current I3 with a prescribed value to flow from output node N2to the ground potential GND line.

The operation of above drive circuit 1 will now be described. In drivecircuit 1, differential amplifier 2 operates to render the potential VMat node N9 equal to the potential at input node N1. More specifically,N-type transistor 6 and P-type transistor 4 are connected in series toeach other, and P-type transistors 3 and 4 form a current mirrorcircuit, such that a current with a value corresponding to the monitorpotential VM flows into P-type transistor 3.

When the monitor potential VM is higher than the input potential VI, thecurrent flowing into P-type transistor 3 becomes larger than the currentflowing into N-type transistor 5, increasing the potential V3 at nodeN3. This reduces the current flowing into P-type transistor 8, therebyreducing the monitor potential VM. When the monitor potential VM issmaller than the input potential VI, the current flowing into P-typetransistor 3 becomes smaller than the current flowing into the N-typetransistor 5, reducing the potential V3 at node N3. This allows largercurrent to flow into P-type transistor 8, increasing the monitorpotential VM. Thus, VM=VI.

The current I2 in constant current circuit 11 is set to a sufficientlysmall value to produce a potential VC at node N8 that satisfies:VC=VM+VTN, where VTN is the threshold voltage of the N-type transistors.Further, the current driving capacity of N-type transistor 10 issufficiently larger than that of constant current circuit 12 such thatN-type transistor 10 operates as a source follower to produce apotential VO at output node N2 that satisfies: VO=VC−VTN=VM=VI. Thisprovides an output potential VO that is equal to the input potential VI.

Now, the relationship between N-type transistors 9, 10 and the currentsI2; I3 in constant current circuits 11, 12 will be described below inmore detail. When the current amplification coefficients of N-typetransistors 9 and 10 are β9 and β10, respectively, the relationshipbetween N-type transistors 9, 10 and the currents I2, I3 in constantcurrent circuits 11, 12 is given by the equations:I 2=β9(VC−VM−VTN)²/2  (1), andI 3=β10(VC−VO−VTN)²/2  (2).Suppose that VM (=VI)=VO, the equation (1) gives the equation:I 2=β9(VC−VO−VTN)²/2  (3).Further, the equations (3) and (2) give the equation:I 2/I 3=β9/β10  (4).In short, I2, I3, β9, and β10 are set to satisfy the equation (4) toachieve VI=VO.

In the first embodiment, the capacitance in the feedback loop todifferential amplifier 2 is the total gate capacitance of N-typetransistors 6, 9 and 10, such that the capacitance in the feedback loopto differential amplifier 2 is significantly small compared with theconventional implementation where the load capacitance was directlyconnected with differential amplifier 131. Thus, oscillation isprevented from occurring in drive circuit 1.

It should be noted that each of field-effect transistors 3 to 6 and 8 to10 may be a MOS transistor or a thin film transistor (TFT). A thin filmtransistor may be formed of any semiconductor thin film, such as apolysilicon thin film, amorphous silicon thin film or the like, and maybe formed on any insulating substrate, such as a resin substrate, glasssubstrate or the like.

FIGS. 2A to 2C are circuit diagrams illustrating the structure ofconstant current circuit 7 shown in FIG. 1. In FIG. 2A, constant currentcircuit 7 includes a resistor 13 and N-type transistors 14 and 15.Resistor 13 and N-type transistor 14 are connected in series between thepower supply potential VDD line and the ground potential GND line, andN-type transistor 15 is connected between node N5 and the groundpotential GND line. N-type transistors 14, 15 have their gates commonlyconnected to the drain of N-type transistor 14. N-type transistors 14and 15 form a current mirror circuit. A constant current with a valuecorresponding to the resistance value of resistor 13 flows into resistor13 and N-type transistor 14. A constant current I1 with a valuecorresponding to the current flowing into N-type transistor 14 flowsinto N-type transistor 15.

In FIG. 2B, constant current circuit 7 includes an N-type transistor 16.N-type transistor 16 is connected between node N5 and the groundpotential GND line and has its gate receiving a constant bias potentialVBN. The bias potential VBN is set to a prescribed level that causesN-type transistor 16 to be operated in a saturation region. Thus, aconstant current I1 flows into N-type transistor 16.

In FIG. 2C, constant current circuit 7 includes a depletion-type N-typetransistor 17. N-type transistor 17 is connected between node N5 and theground potential GND line, and has a gate connected to the groundpotential GND line. N-type transistor 17 is provided to allow a constantcurrent I1 to flow therethrough even when its gate-source voltage is at0 Volt. Constant current circuit 11 may have the same structure asconstant current circuit 7, or may be formed of a resistance elementthat allows the current I2 to flow therethrough. Similarly, constantcurrent circuit 12 may have the same structure as constant currentcircuit 7, or may be formed of a resistance element that allows thecurrent I3 to flow therethrough.

In drive circuit 18 of FIG. 3, power supply potentials V1, V2 and V3that are different from each other are supplied to the sources of P-typetransistors 3, 4, the source of P-type transistor 8, and the drain ofN-type transistor 10, respectively. Further, the low potential terminalsof constant current circuits 7, 11 and 12 are connected to therespective power supply potentials V4, V5 and V6 that are different fromeach other. This variation also provides the same effect as drivecircuit 1 of FIG. 1.

Drive circuit 20 of FIG. 4 has a differential amplifier 21 substitutedfor differential amplifier 2 of drive circuit 1 in FIG. 1. Differentialamplifier 21 has resistors 22 and 23 substituted for P-type transistors3 and 4, respectively, of differential amplifier 2. Resistors 22 and 23are connected between the power supply potential VDD line and nodes N3and N4, respectively.

The sum of the current flowing into N-type transistor 5 and the currentflowing into N-type transistor 6 is equal to the current I1 flowing intoconstant current circuit 7. When the monitor potential VM is equal tothe input potential VI, the current flowing into N-type transistor 5 isequal to the current flowing into N-type transistor 6. When the monitorpotential VM is higher than the input potential VI, the current inN-type transistor 6 is increased while the current in N-type transistor5 is decreased, such that the potential V3 at node N3 is increased,thereby reducing the current in P-type transistor 8, which in turnreduces the monitor potential VM. When the monitor potential VM is lowerthan the input potential VI, the current in N-type transistor 6 isdecreased while the current in N-type transistor 5 is increased, suchthat the potential V3 at node N3 is reduced, thereby increasing thecurrent in P-type transistor 8, which in turn increases the monitorpotential VM. Consequently, the monitor potential VM is maintained atthe same level as the input potential VI, thus achieving VO=VI. Thisvariation also provides the same effect as drive circuit 1 of FIG. 1.

[Second Embodiment]

FIG. 5 is a circuit diagram illustrating the structure of a push-typedrive circuit 25 according to a second embodiment of the presentinvention. In FIG. 5, drive circuit 25 includes a differential amplifier26, constant current circuits 32, 33 and N-type transistors 34 to 36.

Differential amplifier 26 includes a constant current circuit 27, P-typetransistors 28, 29 and N-type transistors 30, 31. Constant currentcircuit 27 is connected between the power supply potential VDD line andnode N27, and allows a constant current I1 with a prescribed value toflow from the power supply potential VDD line to node N27. P-typetransistors 28 and 29 are connected between node N27 and respectivenodes N28 and N29, and have their gates receiving the input potential VIand the monitor potential VM, respectively. N-type transistors 30 and 31are connected between respective nodes N28 and N29 and respective groundpotential GND lines, and have their gates commonly connected to nodeN29. N-type transistors 30 and 31 form a current mirror circuit.

Constant current circuit 32 and N-type transistors 34 and 35 areconnected in series between the power supply potential VDD line and aground potential GND line. Constant current circuit 32 allows a constantcurrent I2 with a prescribed value to flow from the power supplypotential VDD line to node N32. N-type transistor 34 has its gateconnected to its drain (node N32). N-type transistor 34 forms a diode.The potential at node N34 between N-type transistors 34 and 35 definesthe monitor potential VM. The gate of N-type transistor 35 receives thepotential V28 at output node N28 in differential amplifier 26. N-typetransistor 36 is connected between the power supply potential VDD lineand output node N2, and has its gate receiving the potential VC at nodeN32. Constant current circuit 33 is connected between output node N2 anda ground potential GND line, and allows a constant current 13 with aprescribed value to flow from output node N2 to the ground potential GNDline.

The operation of above drive circuit 25 will now be described. In drivecircuit 25, differential amplifier 26 operates to render the monitorpotential VM equal to the input potential VI. More specifically, P-typetransistor 29 and N-type transistor 31 are connected in series andN-type transistors 30 and 31 form a current mirror circuit, such that acurrent with a value corresponding to the monitor potential VM flowsinto N-type transistor 30.

When the monitor potential VM is higher than the input potential VI, thecurrent flowing into N-type transistor 30 becomes smaller than thecurrent flowing into P-type transistor 29, thereby increasing thepotential V28 at node N28. Thus, the current flowing into N-typetransistor 35 is increased and the monitor potential VM is decreased.When the monitor potential VM is lower than the input potential VI, thecurrent flowing into N-type transistor 30 becomes larger than thecurrent flowing into P-type transistor 28 and the potential V28 at nodeN28 is reduced. Thus, the current flowing into MOS transistor 35 isreduced, thereby increasing the monitor potential VM. This results inVM=VI.

The current I2 in constant current circuit 32 is set to a sufficientlysmall value to produce a potential VC at node N32 that satisfies:VC=VM+VTN. Also, the current driving capacity of N-type transistor 36 issufficiently larger than that of constant current circuit 33 to causethe N-type transistor to operate as a source follower to produce apotential VO at output node N2 that satisfies: VO=VC−VTN=VM=VI. Thisprovides an output potential VO at the same level as the input potentialVI.

In the second embodiment, the capacitance in the feedback loop todifferential amplifier 26 is the total gate capacitance of transistors29, 34 and 36, such that the capacitance in the feedback loop todifferential amplifier 26 is sufficiently small compared with theconventional implementation where the load capacitance was directlyconnected with differential amplifier 131. Thus, oscillation isprevented from occurring in drive circuit 25.

FIGS. 6A to 6C are circuit diagrams illustrating the structure ofconstant current circuit 27 shown in FIG. 5. In FIG. 6A, constantcurrent circuit 27 includes P-type transistors 37, 38 and a resistor 39.P-type transistor 37 and resistor 39 are connected in series between thepower supply potential VDD line and the ground potential GND line, andP-type transistor 38 is connected between the power supply potential VDDline and node N27. P-type transistors 37 and 38 have their gatescommonly connected to the drain of P-type transistor 37. P-typetransistors 37 and 38 form a current mirror circuit. A constant currentwith a value corresponding to the resistance value of resistor 39 flowsinto P-type transistor 37 and resistor 39. A constant current I1 with avalue corresponding to the current flowing into P-type transistor 37flows into P-type transistor 38.

In FIG. 6B, constant current circuit 27 includes a P-type transistor 40.P-type transistor 40 is connected between the power supply potential VDDline and node N27, and has its gate receiving a constant bias potentialVBP. The bias potential VBP is set to a prescribed level that causesP-type transistor 40 to be operated in a saturation region. Thus, aconstant value I1 flows into P-type transistor 40.

In FIG. 6C, constant current circuit 27 includes a depletion-type P-typetransistor 41. P-type transistor 41 is connected between the powersupply potential VDD line and node N27, and has its gate connected tothe power supply potential VDD line. P-type transistor 41 is provided toallow a constant current I1 to flow therethrough even when thegate-source voltage is at 0 Volt. Constant current circuit 32 may havethe same structure as constant current circuit 27, or may be formed of aresistance element that allows the current I2 to flow therethrough.

Drive circuit 45 of FIG. 7 has a differential amplifier 46 substitutedfor differential amplifier 26 of drive circuit 25 in FIG. 5.Differential amplifier 46 has resistors 47 and 48 substituted for N-typetransistors 30 and 31, respectively, of differential amplifier 26.Resistors 47 and 48 are connected between respective nodes, N28 and N29,and ground potential GND. The sum of the current flowing into P-typetransistor 28 and the current flowing into P-type transistor 29 is equalto the current I1 flowing into constant current circuit 27. When themonitor potential VM is equal to the input potential VI, the current inP-type transistor 28 is equal to the current in P-type transistor 29.When the monitor potential VM is higher than the input potential VI, thecurrent in P-type transistor 29 is reduced while the current in P-typetransistor 28 is increased such that the potential V28 at node N28 isincreased, thereby increasing the current in N-type transistor 35,reducing the monitor potential VM. When the monitor potential VM islower than the input potential VI, the current in P-type transistor 29is increased while the current in P-type transistor 28 is decreased suchthat the potential V28 at node N28 is reduced, thereby reducing thecurrent in N-type transistor 35, increasing the monitor potential VM.Thus, the monitor potential VM is maintained at the input potential VI,thus achieving VO=VI. This variation provides the same effect as drivecircuit 1 of FIG. 1.

Drive circuit 50 in FIG. 8 has differential amplifier 2 of FIG. 1substituted for differential amplifier 26 of drive circuit 25 of FIG. 5.N-type transistor 35 has its gate receiving the potential V3 at node N3,while N-type transistor 6 has its gate receiving the monitor potentialVM. When the monitor potential VM is higher than the input potential VI,the current flowing into P-type transistor 3 becomes larger than thecurrent flowing into P-type transistor 5, which increases the potentialV3 at node N3, such that the current in N-type transistor 35 isincreased, thereby reducing the monitor potential VM. When the monitorpotential VM is lower than the input potential VI, the current flowinginto P-type transistor 3 becomes smaller than the current flowing intoN-type transistor 5, which reduces the potential V3 at node N3, suchthat the current in N-type transistor 35 is decreased, therebyincreasing the monitor potential VM. Thus, VM=VI and therefore VO=VI.This variation also provides the same effect as drive circuit 25 in FIG.5.

[Third Embodiment]

FIG. 9 is a circuit diagram showing the structure of a pull type drivecircuit 55 according to a third embodiment of the present invention. InFIG. 9, drive circuit 55 includes a differential amplifier 2, P-typetransistors 56 to 58 and constant current circuits 59, 60. Differentialamplifier 2 is the same as in FIG. 1. P-type transistors 56, 57 andconstant current circuit 59 are connected in series between the powersupply potential VDD line and a ground potential GND line. P-typetransistor 56 has its gate receiving the potential V3 at node N3. N-typetransistor 6 has its gate receiving the potential VM at node N56 betweenP-type transistors 56 and 57. P-type transistor 57 has its gateconnected to its drain (node N57). P-type transistor 57 forms a diode.Constant current circuit 59 allows a constant current I2 with aprescribed value to flow from node N57 to the ground potential GND line.Constant current circuit 60 allows a constant current 13 with aprescribed value from the power supply potential VDD line to output nodeN2. P-type transistor 58 is connected between output node N2 and aground potential GND line and has its gate receiving the potential VC atnode N57.

The monitor potential VM is maintained at the input potential VI bymeans of the operation of differential amplifier 2. The current drivingcapacity of P-type transistor 57 is sufficiently larger than theconstant current 12 in constant current circuit 59 to produce apotential VC at node N57 that satisfies: VC=VM−|VTP|, where VTP is thethreshold voltage of the P-type transistors. The current drivingcapacity of P-type transistor 58 is sufficiently larger than theconstant current 13 in constant current circuit 60 to produce an outputpotential VO that satisfies: VO=VC+|VTP|=VM−|VTM|+|VTP|=VM=VI.

In the third embodiment, the capacitance in the feedback loop todifferential amplifier 2 is the total gate capacitance of transistors 6,57 and 58, such that the capacitance in the feedback loop todifferential amplifier 2 is sufficiently small compared to theconventional implementation where the load capacitance was directlyconnected with differential amplifier 131. Thus, oscillation isprevented from occurring in drive circuit 55.

Drive circuit 61 of FIG. 10 has differential amplifier 26 substitutedfor differential amplifier 2 of drive circuit 55 in FIG. 9. P-typetransistor 56 has its gate receiving the potential V28 at node N28.P-type transistor 29 has its gate receiving the monitor potential VM.When the monitor potential VM is higher than the input potential VI, thecurrent in N-type transistor 30 becomes smaller than the current inP-type transistor 28, which increases potential V28 at node N28, suchthat the current flowing through P-type transistor 56 is decreased,reducing the monitor potential VM. When the monitor potential VM islower than the input potential VI, the current in N-type transistor 30becomes larger than the current in P-type transistor 28, which reducesthe potential V28 at node N28, such that the current flowing throughP-type transistor 56 is increased, thereby increasing the monitorpotential VM. Thus, VM=VI and therefore VO=VI. This variation alsoprovides the same effect as drive circuit 55 in FIG. 9.

Drive circuit 65 in FIG. 11 has a constant current circuit 66 and anN-type transistor 67 substituted for P-type transistor 56 and constantcurrent circuit 59, respectively, of drive circuit 61 in FIG. 10.Constant current circuit 66 allows a constant current I2 with aprescribed value to flow from the power supply potential VDD line tonode N56. N-type transistor 67 is connected between node N57 and aground potential GND line and has its gate receiving the potential V28at node N28. When the monitor potential VM is higher than the inputpotential VI, the potential V28 at node N28 is increased, whichincreases the current flowing into N-type transistor 67, reducing themonitor potential VM. When the monitor potential VM is lower than theinput potential VI, the potential V28 at node N28 is reduced, whichreduces the current flowing into N-type transistor 67, increasing themonitor potential VM. Thus, VM=VI and therefore VO=VI. This variationalso provides the same effect as drive circuit 55 of FIG. 9.

[Fourth Embodiment]

FIG. 12 is a circuit diagram showing the structure of a push type drivecircuit 70 with offset compensation capability according to a fourthembodiment of the present invention. In FIG. 12, push type drive circuit70 with offset compensation capability includes a drive circuit 1, acapacitor 71 and switches S1–S3. Drive circuit 1 is the same as inFIG. 1. Capacitor 71 and switches S1–S3 define an offset compensationcircuit for compensating for an offset voltage VOF, i.e. the differencebetween the input potential VI and the output potential VO in FIG. 1caused by a variation in the threshold voltage of the transistors indrive circuit 1.

More specifically, switch S1 is connected between input node N1 and thegate of N-type transistor 5. Capacitor 71 and switch S2 are connected inseries between the gate of N-type transistor 5 and output node N2, andswitch S3 is connected between the input node N1 and a node betweencapacitor 71 and switch S2. Each of switches S1–S3 may be a P-type orN-type transistor, or may be provided by P-type and N-type transistorsconnected in parallel. Each of switches S1–S3 is on/off controlled by acontrol signal (not shown).

The following description illustrates the case in which the outputpotential VO of drive circuit 1 is lower than the input potential VI bythe offset voltage VOF. In their initial state, all of switches S1–S3are off, and when switches S1 and S2 are turned on at a certain time,the output potential VO is given by: VO=VI−VOF, and capacitor 71 ischarged to the offset voltage VOF.

Next, when switches S1 and S2 are turned off, the offset voltage VOF isretained in capacitor 71. Subsequently, if switch S3 is on, the gatepotential of N-type transistor 5 is given by: VI+VOF. As a result, theoutput potential VO of drive circuit 1 is given by: VO=VI+VOF−VOF=VI,which means that the offset voltage VOF of drive circuit 1 has beeneliminated.

In the fourth embodiment, the offset voltage VOF of drive circuit 1 canbe eliminated, thereby enabling the output potential VO to be preciselymatched with the input potential VI.

It should be noted that the fourth embodiment illustrates theelimination of the offset potential VOF for drive circuit 1, althoughemploying the same method can naturally eliminate the offset voltage VOFfor any of drive circuits 18, 20, 25, 45, 50, 55, 61, and 65.

[Fifth Embodiment]

In drive circuit 1 of FIG. 1, the current I11 in constant currentcircuit 11 is set to a small value such that, when the input potentialVI decreases, the decrease in the potential VC at node N8 takes time,and thus the output potential VO is decreased slowly. The fifthembodiment solves this problem.

FIG. 13 is a circuit diagram illustrating the structure of drive circuit75 according to the fifth embodiment of the present invention. Referringto FIG. 13, drive circuit 75 is different from drive circuit 1 of FIG. 1in that an additional N-type transistor 76 is provided. N-typetransistor 76 is connected in parallel with constant current circuit 11,and has its gate receiving the signal φPD.

The signal φPD is rendered to a “high” level in a pulsing manner inresponse to a decrease in the input potential VI. Thus, N-typetransistor 76 conducts in a pulsing manner, such that the potential VCat node N8 is decreased rapidly, which in turn rapidly decreases theoutput potential VO.

It should be noted that, although the fifth embodiment has the source ofN-type transistor 76 connected to the ground potential GND line, it isnot limited thereto and the source of N-type transistor 76 may beconnected to other potential lines to decrease the potential at node N8to a prescribed level.

Further, N-type transistor 76 may be substituted with a P-typetransistor. In this case, the signal φPD needs to be rendered to a “low”level in a pulsing manner in response to a decrease in the inputpotential VI.

N-type transistor 76 may also be connected to constant current circuit59 of drive circuit 55 in FIG. 9 to provide the same effect.

[Sixth Embodiment]

In drive circuit 25 of FIG. 5, the current I2 in constant currentcircuit 32 is set to a small value such that, when the input potentialVI is increased, the increase in the potential VC at node N32 takes timeand thus the output potential VO is increased slowly. The sixthembodiment attempts to solve this problem.

FIG. 14 is a circuit diagram showing the structure of a drive circuit 80according to the sixth embodiment of the present invention. Referring toFIG. 14, drive circuit 80 is different from drive circuit 25 of FIG. 5in that an additional P-type transistor 81 is provided. P-typetransistor 81 is connected in parallel with constant current circuit 32and has its gate receiving the signal φPU. The signal φPU is rendered toa “low” level in a pulsing manner in response to an increase in theinput potential VI. Thus, P-type transistor 81 conducts in a pulsingmanner and the potential VC at node N32 is increased rapidly, which inturn rapidly increases the output potential VO.

It should be noted that, although the sixth embodiment has the source ofP-type transistor 81 connected to the power supply potential VDD line,it is not limited thereto and the source of P-type transistor 81 may beconnected to other potential lines to increase the potential at node N32to a prescribed level.

Further, P-type transistor 81 may be substituted with an N-typetransistor. In this case, the signal φPU needs to be rendered to a“high” level in a pulsing manner in response to a decrease in the inputpotential VI.

P-type transistor 81 may also be connected to constant current circuit66 of drive circuit 65 in FIG. 11 to provide the same effect.

[Seventh Embodiment]

FIG. 15 is a circuit diagram showing the structure of a push-pull typedrive circuit 85 according to a seventh embodiment of the presentinvention. In FIG. 15, drive circuit 85 is a combination of push typedrive circuit 1 of FIG. 1 and pull type drive circuit 65 of FIG. 11.Input node N1 of push type drive circuit 1 is connected with input nodeN1 of pull type drive circuit 65, while output node N2 of push typedrive circuit 1 is connected with output node N2 of pull type drivecircuit 65.

When the output potential VO is higher than the input potential VI, thegate-source voltage of N-type transistor 10 in push type drive circuit 1becomes smaller than the threshold voltage VTN of N-type transistor 10and thus N-type transistor 10 becomes non-conductive, while thesource-gate voltage of P-type transistor 58 in pull type drive circuit65 becomes larger than the absolute value of the threshold voltage VTPof P-type transistor 58 and thus P-type transistor 58 becomesconductive, thereby reducing the output potential VO.

When the output potential VO is lower than the input potential VI, thesource-gate voltage of P-type transistor 58 in push type drive circuit 1becomes smaller than the absolute value of the threshold VTP of P-typetransistor 58 and thus P-type transistor 58 becomes non-conductive,while the gate-source voltage of N-type transistor 10 of pull type drivecircuit 65 becomes larger than the threshold VTN of N-type transistor 10and thus N-type transistor 10 becomes conductive, increasing the outputpotential VO. Thus, VO=VI.

The seventh embodiment provides the same effect as the first embodimentand provides a large current driving capacity both when output node N2is charged and discharged.

Different variations of the present embodiment will now be described.Push-pull type drive circuit 90 of FIG. 16 is a combination of push typedrive circuit 25 of FIG. 5 and pull type drive circuit 55 of FIG. 9.Input node N1 of push type drive circuit 25 is connected to input nodeN1 of pull type drive circuit 55, while output node N2 of push typedrive circuit 25 is connected to output node N2 of pull type drivecircuit 55. This variation also provides the same effect as drivecircuit 85 of FIG. 15.

Push-pull type drive circuit 95 of FIG. 17 is a combination of push typedrive circuit 1 of FIG. 1 and pull type drive circuit 55 of FIG. 9.Push-pull type drive circuit 96 of FIG. 18 is a combination of push typedrive circuit 25 of FIG. 5 and pull type drive circuit 65 of FIG. 11.These variations, too, provide the same effect as drive circuit 85 ofFIG. 15.

[Eighth Embodiment]

FIG. 19 is a circuit diagram showing the structure of push-pull typedrive circuit 100 according to an eighth embodiment of the presentinvention. Referring to FIG. 19, drive circuit 100 has P-typetransistors 101 and 102 added to drive circuit 1 of FIG. 1. P-typetransistor 101 and constant current circuit 11 are connected in seriesbetween node 9 and a ground potential GND line, and P-type transistor101 has its gate connected to its drain (node N101). P-type transistor101 forms a diode. P-type transistor 102 is connected between outputnode N2 and a ground potential GND line, and has its gate receiving thepotential VC1 at node N101.

The operation of differential amplifier 2 provides a potential at nodeN9, VM, that satisfies: VM=VI. Thus, the potential VC at node N8 isgiven by: VC=VI+VTN and the potential VC1 at node N101 is given by:VC1=VI−|VTP|. When the output potential VO is higher than the inputpotential VI, N-type transistor 10 becomes non-conductive while P-typetransistor 102 becomes conductive. When the output potential VO is lowerthan the input potential VI, P-type transistor 102 becomesnon-conductive while N-type transistor 10 becomes conductive. Thus,VO=VI.

The eighth embodiment provides the same effect as the seventh embodimentand provides a reduced layout area because the differential amplifiersare combined into one.

[Ninth Embodiment]

FIG. 20 is a circuit diagram showing the structure of a push-pull typedrive circuit 105 according to a ninth embodiment of the presentinvention. Referring to FIG. 20, drive circuit 105 has N-typetransistors 106 and 107 added to drive circuit 65 of FIG. 11. Constantcurrent circuit 66 and N-type transistor 106 are connected in seriesbetween the power supply potential VDD line and node N56, and N-typetransistor 106 has its gate connected to its drain (node N66). N-typetransistor 106 forms a diode. N-type transistor 107 is connected betweenthe power supply potential VDD line and output node N2, and has its gatereceiving the potential VC1 at node N66. The operation of differentialamplifier 26 provides a potential at node N56, VM, that satisfies:VM=VI. Accordingly, the potential VC1 at node N66 is given by:VC1=VI+VTN, while the potential VC at node N57 is given by: VC=VI−|VTP|.When the output potential VO is higher than the input potential VI,N-type transistor 107 becomes non-conductive, while P-type transistor 58becomes conductive. When the output potential VO is lower than the inputpotential VI, P-type transistor 58 becomes non-conductive while N-typetransistor 107 becomes conductive. Thus, VO=VI.

The ninth embodiment also provides the same effect as the eighthembodiment.

[Tenth Embodiment]

FIG. 21 is a circuit diagram showing the structure of push-pull typedrive circuit 110 with offset compensation capability according to atenth embodiment of the present invention. In FIG. 21, drive circuit 110includes drive circuit 1 of FIG. 1, drive circuit 65 of FIG. 11,capacitors 111 a and 111 b, switches S1 a–S4 a, and S1 b–S4 b.

Switches S1 a and S1 b are connected between input node N1 and the gatesof N-type transistor 5 and P-type transistor 28 of drive circuits 1 and65, respectively. Capacitor 111 a and switch S2 a are connected inseries between the gate of N-type transistor 5 of drive circuit 1 andthe source of N-type transistor 10 (node N10). Capacitor 111 b andswitch S2 b are connected in series between the gate of P-typetransistor 28 of drive circuit 65 and the source of P-type transistor 58(node N60). Switch S3 a is connected between input node N1 and a nodebetween capacitor 111 a and switch S2 a. Switch S3 b is connectedbetween input node N1 and a node between capacitor 111 b and switch S2b. Switches S4 a and S4 b are connected between respective nodes, N10and N60, and output node N2.

The operation of drive circuit 110 will now be described. In theirinitial state, all of switches S1 a–S4 a and S1 b–S4 b are off. Whenswitches S1 a, S2 a, S1 b, and S2 b are turned on at a certain time, thepotentials V10 and V60 at nodes N16 and N60 are given by: V10=VI−VOFaand V60=VI−VOFb, respectively, and capacitors 111 a, 111 b are chargedto their respective offset voltages VOFa and VOFb.

Then, when switches S1 a, S2 a, S1 b, and S2 b are turned off, theoffset voltages VOFa, VOFb are retained in capacitors 111 a and 111 b,respectively. Then, when switches S3 a, S3 b are turned on, the gatevoltages of N-type transistor 5 and P-type transistor 28 of drivecircuits 1, 65 are given by: VI+VOFa and VI+VOFb, respectively. As aresult, the output potentials V10, V60 of their respective drivecircuits 1, 65 are given by: V10=VI+VOFa−VOFa=VI andV60=VI+VOFb−VOFb=VI, thereby eliminating the offset voltages VOFa, VOFbof their respective drive circuits 1, 65. Finally, switches S4 a, S4 bare turned on such that VO=VI.

The tenth embodiment provides a drive circuit 110 with no offset voltageand of high current driving capacity during charging and discharging.

It should be understood that the disclosed embodiments are, in allrespects, by way of illustration and example only and are not by way oflimitation. The scope of the present invention is set forth by theclaims rather than the above description and is intended to include allthe modifications within the spirit and scope equivalent to those of theclaims.

1. A drive circuit outputting to an output node a potentialcorresponding to an input potential, comprising: a first sub-drivecircuit including: a first transistor of a first conductivity typeconnected between a first power supply potential line and a first node;a second transistor of the first conductivity type having a gate and afirst electrode connected to a gate of said first transistor, and asecond electrode connected to a second node; a third transistorconnected in series with said second transistor between second and thirdpower supply potentials lines; and a first differential amplifier forregulating a gate potential of said third transistor to match apotential at said second node with said input potential; a secondsub-drive circuit including: a fourth transistor of a secondconductivity type connected between a fourth power supply potential linedifferent from said first power supply potential and a third node; afifth transistor of a second conductivity type having a gate and a firstelectrode connected to a gate of said fourth transistor, and a secondelectrode connected to a fourth node; a sixth transistor connected inseries with said fifth transistor between said second and third powersupply potential lines; and a second differential amplifier forregulating a gate potential of said sixth transistor to match apotential at said fourth node with said input potential; a first offsetcompensation circuit for eliminating an offset voltage of said firstsub-drive circuit and connecting said first node to said output node;and a second offset compensation circuit for eliminating an offsetvoltage of said second sub-drive circuit and connecting said third nodeto said output node.
 2. The drive circuit according to claim 1, whereinsaid third transistor is connected between said second power supplypotential line and the first electrode of said second transistor, saidfirst sub-drive circuit further includes a current limiting elementconnected between said second node and said third power supply potentialline.
 3. The drive circuit according to claim 2, wherein said firstsub-drive circuit further includes a switching element connected inparallel with said current limiting element to conduct in a pulsingmanner with prescribed timing.
 4. The drive circuit according to claim1, wherein said third transistor is connected between said second nodeand said third power supply potential line, said first sub-drive circuitfurther includes a current limiting element connected between saidsecond power supply potential line and the first electrode of saidsecond transistor.
 5. The drive circuit according to claim 4, whereinsaid first sub-drive circuit further includes a switching elementconnected in parallel with said current limiting element to conduct in apulsing manner with prescribed timing.
 6. The drive circuit according toclaim 1, wherein said third transistor is connected between said secondpower supply potential line and the first electrode of said secondtransistor, said sixth transistor is connected between said third powersupply potential line and the first electrode of said fifth transistor,said first sub-drive circuit further includes: a first current limitingelement connected between said second node and said third power supplypotential line, and said second sub-drive circuit further includes asecond current limiting element connected between said fourth node andsaid second power supply potential line.
 7. The drive circuit accordingto claim 1, wherein said third transistor is connected between saidsecond node and said third power supply potential line, said sixthtransistor is connected between said fourth node and said second powersupply potential line, said first sub-drive circuit further includes: afirst current limiting element connected between said second powersupply potential line and the first electrode of said second transistor,and said second sub-drive circuit further includes a second currentlimiting element connected between said third power supply potentialline and the first electrode of said fifth transistor.
 8. The drivecircuit according to claim 1, wherein said third transistor is connectedbetween said second power supply potential line and the first electrodeof said second transistor, said sixth transistor is connected betweensaid fourth node and said second power supply potential line, said firstsub-drive circuit further includes a first current limiting elementconnected between said second node and said third power supply potentialline, and said second sub-drive circuit further includes a secondcurrent limiting element connected between said third power supplypotential line and the first electrode of said fifth transistor.
 9. Thedrive circuit according to claim 1, wherein said first offsetcompensation circuit includes: a first current limiting elementconnected between said first node and a sixth power supply potentialline; a first capacitor; a first switching circuit for providing saidinput potential to one electrode of said first capacitor and connectingthe other electrode of said first capacitor to said first node; a secondswitching circuit for providing said input potential to the otherelectrode of said first capacitor and providing, instead of said inputpotential, a potential of the one electrode of said first capacitor tosaid first differential amplifier; and a third switching circuit forproviding a potential at said first node to said output node, and saidsecond offset compensation circuit includes: a second current limitingelement connected between said third node and a seventh power supplypotential line; a second capacitor; a fourth switching circuit forproviding said input potential to one electrode of said second capacitorand connecting the other electrode of said second capacitor to saidthird node; a fifth switching circuit for providing said input potentialto the other electrode of said second capacitor and providing, insteadof said input potential, a potential of the other electrode of saidsecond capacitor to said second differential amplifier; and a sixthswitching circuit for providing a potential at said third node to saidoutput node.
 10. The drive circuit according to claim 1, wherein saidfirst differential amplifier includes: seventh and eighth transistorshaving gates receiving the input potential and a potential at saidsecond node, respectively, and first electrodes connected to each other;ninth and tenth transistors of a conductivity type different from thatof said seventh and eighth transistors, connected between a fourth powersupply potential line and second electrodes of said seventh and eighthtransistors, respectively, and having gates connected to the secondelectrode of said eighth transistor; and a current limiting elementconnected between the first electrodes of said seventh and eighthtransistors and a fifth power supply potential line.
 11. The drivecircuit according to claim 10, wherein said first, second and fourthpower supply potentials are the same potential, and said third and fifthpower supply potentials are the same potential.
 12. The drive circuitaccording to claim 10, wherein said first, second and fifth power supplypotentials are the same potential, and said third and fourth powersupply potentials are the same potential.
 13. The drive circuitaccording to claim 1, wherein said first differential amplifierincludes: seventh and eighth transistors having gates receiving saidinput potential and a potential at said second node, respectively, andfirst electrodes connected to each other; first and second resistorsconnected between a fourth power supply potential line and secondelectrodes of said seventh and eighth transistors, respectively; and acurrent limiting element connected between the first electrodes of saidseventh and eighth transistors, respectively, and a fifth power supplypotential line.
 14. The drive circuit according to claim 1, wherein eachof said first to sixth transistors is a thin film transistor.